ABEL™
ABEL is a Hardware Description Language (HDL). It features boolean equations, truth tables and state diagrams. An ABEL-HDL design file is the source for the compiler.
ACW (Architecture Control Word)
Output configurations are controlled by a set of fuses, i.e. programmable ACW cells. The composition of the fuses within the ACW is device specific.
Bulk Erase
Bulk Erase resets all bits of the AND array, ACW, UES and Security Cell to ‘1’. The PES is not affected.
Device Code
Unique GAL device type number (8-bit hex).
It is stored in the PES, byte 2 (bit16..23).
Device Mode
Two bits, SYN & AC0, in the ACW define the three valid device modes Simple, Complex and Registered. This applies only to GAL16V8 & GAL20V8. Modes and conditions, depending on your logic design:
Simple Mode
– No tri-state output with output enable
– No registered output (no D-FF, register in use)
Usable product terms per output: 8
Complex Mode
– At least one tri-state output with output enable
– No registered output (no D-FF, register in use)
Usable product terms per output: 7
(1 product term reserved for output enable)
Registered Mode
– At least one registered output (D-FF, register in in the OLMC is in use)
Usable product terms per registered output: 8
(registered outputs: CLK source is pin1, Output Enable source is pin11/13)
Usable product terms per combinatorial output: 7
(1 product term reserved for output enable)
Fuse
A GAL-Fuse represents a conducting or non-conducting connection by an EEPROM cell between on-chip logic, depending on the programmed Fuse state data (see Fuse Map).
GAL: reprogrammable
PAL: OTP-Fuse (e.g. tungsten), One Time Programmable to non-conducting state (‘blown’)
Fuse Map
The Fuse Map is the main part of the JEDEC-file. It represents all functionally relevant programmable fuses of the device. And, where applicable, extended by UES, Power down, etc. fuses.
‘1’ non-conducting (blown fuse)
‘0’ conducting (intact fuse)
The fuses in the Fuse Map are numbered from 0 to a device dependent total of N. Specific information on fuse functions can be found in the data sheet.
GAL Logic Diagram (simplified example):
IN1 -----------+--|>o
IN0 -+--|>o | |
| | | |
0 1 2 3 ___
0--+----+----+----+----|_&_|- H (all fuses blown)
| | | | ___
4--X----X----X----X----|_&_|- L (all fuses intact)
| | | | ___
8--+----X----X----+----|_&_|- /IN0 & IN1
| | | | ___
12--X----+----+----X----|_&_|- IN0 & /IN1
GAL Fuse Map for the example above:
L0000 1111
L0004 0000
L0008 1001
L0012 0110GAL (Generic Array Logic)
Reprogrammable logic device with 8 to 12 outputs. Each output (OLMC) can utilize one register (D-FF).
JEDEC
Defines a human readable format (ASCII text) for the transfer of information between a data preparation system and a logic device programmer.
The general file format for Fuse Maps. File extension: .JED
OLMC (Output Logic Macro Cell)
Provides Register, feedback, XOR and other I/O capabilities.
OLMC overview for GAL16V8 & GAL20V8 below:
It comprises the FMUX, PTMUX, OMUX, TSMUX, OR gate, polarity XOR gate, D-FF and the Tri-State buffer.
Output MUX (OMUX)
Selects either registered (D-FF) or combinatorial (D-FF bypassed) for the output.
Feedback MUX (FMUX)
The FMUX feeds either the (D-FF) Q- or pin-signal of each OLMC back into the AND array.
Tristate MUX (TSMUX)
Selects one of the four signals below to control the Tri-State buffer.
Simple mode input, output: GND, Vcc
Complex mode: Product Term
Registered mode: Product Term or OE (pin11/pin13)
Product Term MUX (PTMUX)
In Complex and Registered (combinatorial outputs only) mode:
The first product term (PT0) of an OLMC determines the output enable.
This reduces the usable product terms from 8 to 7.
The PTMUX keeps PT0 (output enable) from OR-ing with PT1..PT7.
In Simple mode:
The PTMUX allows OR-ing of PT0 along with PT1..PT7.
PAL (Programmable Array Logic)
One time Programmable Array Logic. Predecessor of the GAL with fixed output functionality instead of an OLMC.
PES (Programmer Electronic Signature)
The factory-programmed PES contains several bytes of crucial information for the GAL programmer. Vendor code, device code, programming algorithm are the most important ones.
PES data is always available to the user independent of the state of the security cell.
PLD (Programmable Logic Device)
Programmable logic devices are essentially uncommitted logic gates where the user determines the final logic configuration of the device. The internal structure of these devices is a fuse-programmable interconnection of AND gates, OR gates, and Registers. These devices allow the user to design combinatorial as well as sequential circuits.
Programmable Output Polarity
In the ACW one XOR(#OLMC) bit for each OLMC defines the output polarity.
Product Term
In the GAL Logic Diagram above one row represents one product term. For instance the product term ‘IN0 AND /IN1’ is represented by row 4, starting at fuse #12.
Product Term Disables
Applies to GAL16V8 & GAL20V8 only.
Feature for reduced power consumption.
In the ACW one PTD(#0..63) bit enables or disables the respective product term.
Security Cell
One bit which prevents the AND array from being read. Reset by Bulk Erase.
PES, UES and ACW can still be read with Security active.
UES (User Electronic Signature)
Reprogrammable memory that can contain user defined data. It has no impact on functionality. Find the UES size by device below.
40 bits: GAL20XV10
64 bits: GAL16V8, GAL20V8, GAL18V10, GAL20RA10, GAL22V10, GAL26V12, GAL26CV12, ATF16V8, ATF20V8, ATF22V10
72 bits: GAL6001, GAL6002
UES data is always available to the user independent of the state of the security cell.
GALs and compatible devices without UES:
GAL22CV10 (National), PALCE22V10 (AMD/VANTIS)