The Analog to Digital Converter (ADC) is similar to the ones used in DMMs by Rhode & Schwarz (UDS 5) and Solartron (7150). It’s a Voltage-To-Time converter like other integrating conversion methods, e.g. Dual Slope.
This Voltage-To-Time converter circuit, comprising an integrator, a comparator, reference switching, converts the voltage output from the buffer amplifier into a PWM signal.
I_IN
V_IN is the unknown voltage to be measured. I_IN is one of the three bipolar input currents to the integrator. It is calculated to I_IN=V_IN/R_IN. Where I_IN with respect to the other input currents defines the range of this Voltage-To-Time converter. The NanoDMM is specified with a range of V_IN = ±2.8V.
I_STEER
This current, with its polarity controlled by the comparator, automatically aligns the output voltage waveform with GND. The frequency of I_STEER is determined by F_FORCE. If V_IN = 0V with respect to GND then the duty cycle of I_STEER is 50%.
I_FORCE
The direction of the integrator output voltage ramping is determined by the dominant I_FORCE. In order to achieve best 50 Hz and 60 Hz noise rejection F_FORCE is set to 300Hz.
Conditions to be met:
I_FORCE > I_STEER > I_IN (absolute values)
I_FORCE > (I_STEER + I_IN) (absolute values)
Current ratios:
I_STEER ca. 0.5 * I_FORCE
I_IN(max) ca. 0.5 * I_STEER
V_COMP
The duty cycle of this PWM signal is proportional to the input voltage V_IN.
ADC count
One ADC period is 1/(300 Hz) = 3.333 ms. Pulse duration t_on of V_COMP for the V_IN range above is ca. 500 us < ton < 2.8 ms giving a captured count N of ca. 8000 < N < 44800. The 4.5 digits resolution of the NanoDMM requires multiple ADC periods to obtain a sufficient total count. One ADC cycle sums 60 ADC periods (= 200ms/3.333ms) to a total count 8000*60 < Ntotal < 60*44800.
Due to comparator jitter, a not to clock synchronized I_STEER and other imperfections an effective result is obtained by reducing the final reading to 4.5 digits.
ADC reading
An ADC reading is calculated from one ADC cycle with V_IN=0V followed by one ADC cycle with V_IN=Vx. Each taking 200 ms.
Vx= (N_total(Vx) – N_total(0V))/ADC_slope
Remarks:
N_total(0V) is needed for the offeset correction.
ADC_slope [COUNTS/V] is obtained during the NanoDMM start-up.
Final reading
The Final Reading takes a factor depending on the selected range and a calibration factor into account.
Reading= ADC Reading * Range Factor * CAL Factor
Design considerations
The ADC is the heart of a DMM. Its performance has an impact on all voltage, current and ohms ranges. The implementation of the ADC needs very few microprocessor resources, I/Os and IRQ handler time.
Integrator Operation
It’s integrating up and down continuously within the supply rails. The summing node of I_IN, I_STEER and I_FORCE is near 0V during linear operation. Any malfunction, including an input overdrive, will drive its output into one of the supply rails.
Integrator Settling
The settling of the integrator and its related conversion error have been analyzed by
I. Yu. Sergeev in “ANALYSIS OF AN ANALOG-DIGITAL CONVERTER WITH A DYNAMIC INTEGRATOR”. Its output signal is sufficiently settled after 5 ADC periods. Therefore an ADC cycle is started 30 ms after switching the front-end mux.
Integrator Overdrive
When increasing the integrator’s input voltage beyond 4.0 V (absolute) its output starts clipping and additionally beyond 4.5 V fails to cross zero volts. Without zero crossing the software assumes a minimum or maximum count depending on the comparator’s output state.
Simulation
