GAL specific information

Introduction

This information is related to the programming mode of the PLDs listed below. Find more details in the Download section.

GAL pinouts for EDIT mode

  • GAL16V8/ATF16V8
  • GAL20V8/ATF20V8
  • GAL22V10/ATF22V10
  • GAL20XV10
  • GAL20RA10
  • GAL18V10
  • GAL26V12C
  • GAL26CV12
  • GAL6001
  • GAL6002

GAL/ATF Architecture

  • 16V8 & 20V8 detailed ACW bit information
  • 16V8, 20V8 & 22V10 Row Addresses Map Block Diagram
                 GAL22V10 Row Addresses Map Block Diagram
         ___________________________________________________
SDIN--->|MSB                                             LSB|-->SDOUT
SCLK----|>                 SHIFT REGISTER                   |
        |___________________________________________________|

    ROW: ___________________________________________________
        |ADDRESS*   |              DATA                     |
      0 |(6 BITS)   |           (132 BITS)                  |
        |-----------+---------------------------------------|
        |DEC; BIN:  |   AND ARRAY, AR, AP; (132 BITS x 44)  |
        |00;000000  |#5764, #5720,      ...         #44, #0 |
        |01;000001  |#5765, #5721,      ...         #45, #1 |
        |   ...     |                   ...                 |
        |43;101011  |#5807, #5763,      ...         #87, #43|
        |-----------+---------------------------------------|
        |           |   ELECTRONIC SIGNATURE (UES 64 BITS)  |
        |44;101100  |GAL22V10: 68x '0', #5891,  ...    #5828|
        |           |ATF22V10: #5891,   ...  #5828, 68x '0' |
        |-----------+---------------------------------------|
        |           |PROGR. ELECTR. SIGNATURE (PES 80 BITS) |
        |58;111010  |           52x '0', PES                |
        |-----------+---------------------------------------|
        |           |           SECURITY CELL               |
        |61;111101  |               132x '0'                |
        |___________|_______________________________________|
         * ATF22V10: reverse bit order, no CLK for 6th adr. bit
         ___________________________________________________
     16 |      ARCHITECTURE CONTROL WORD (ACW 20 BITS)      |
        |PIN14(S0,S1),	PIN15(S0,S1)  ...       PIN23(S0,S1)|
        |#5826,#5827, #5824,#5825,    ...        #5808,#5809|
        |___________________________________________________|
         ___________________________________________________
     59 | ATF22(L)V10C ONLY: DISABLE POWER DOWN (SDIN='0')  |
        |___________________________________________________|
         ___________________________________________________
     61 |             BULK ERASE (SDIN='0')                 |
        |___________________________________________________|

Download section

GAL specific

News

07/2021: GAL18V10 pinout corrected