1541 Memory Map
1541 1541C 1541-II
0000-07FF RAM 0000-07FF RAM 0000-07FF RAM
0800-0FFF RAM mirror
1800-1BFF 6522 VIA1 1000-1BFF 6522 VIA1 1800-1BFF 6522 VIA1
1C00-1FFF 6522 VIA2 1C00-1FFF 6522 VIA2 1C00-1FFF 6522 VIA2
C000-DFFF ROM1 8KB 8000-BFFF ROM mirror
E000-FFFF ROM2 8KB C000-FFFF ROM 16KB C000-FFFF ROM 16KB
1571 Memory Map
1571/C128D C128DCR
0000-07FF RAM 0000-07FF RAM
0800-0FFF RAM mirror
1000-1BFF 6522 VIA1 1800-180F 6522 VIA1
1C00-1FFF 6522 VIA2 1C00-1C0F 6522 VIA2
2000-3FFF WD177X FDC 2000-2005 5710 FDC
4000-7FFF 6526 CIA 400C-400E 5710 CIA Serial Port
4010-4017 5710 FDC2
6000-7FFF RAM mirror
8000-FFFF ROM 32KB 8000-FFFF ROM 32KB
1581 Memory Map
0000-1FFF RAM 8KB
4000-5FFF 8520 CIA
6000-7FFF WD177X FDC
8000-FFFF ROM 32KB
‘Boost Your 1571’ Memory Map
1541/1571 MODE 1581 MODE
0000-0FFF RAM 4KB 0000-3FFF RAM 16KB
1000-1BFF 6522 VIA1
1C00-1FFF 6522 VIA2
2000-3FFF WD177X FDC
4000-4FFF 6526 CIA 4000-5FFF 6526/8520 CIA
5000-7FFF RAM 12KB 6000-7FFF WD177X FDC
8000-FFFF ROM 32KB 8000-FFFF ROM 32KB
DOS sector layout
Component Bytes (GCR) Bytes (non-GCR)
SYNC 5 5 * $FF
HEADER 10 8 > $08, chksum [], [Sector, Track, ID2, ID1], $0F, $0F
GAP1 9 9 * $55
SYNC 5 5 * $FF
DATA 325 260 > $07, 256*Data, checksum of Data, $00, $00
GAP2* 4 4 * $55
------------------------------------
Sector: 358 291
*GAP2 quantity can range from 2 up to about 20, depending on actual track capacity
HW Bit Timing
disk speed [rpm] 300
rotation time [s] 0.2
SYNC detec. [bits] 10
Parameter bitrate3 bitrate2 bitrate1 bitrate0
VIA PB6 1 1 0 0
VIA PB5 1 0 1 0
Sectors 21 19 18 17
Bit Rate [bit/s] 307692 285714 266667 250000
Byte Rate [byte/s] 38461.5 35714.25 33333.38 31250
Bit Time [us] 3.25 3.5 3.75 4
Byte Time [us] 26 28 30 32
Sync Time [us] 102.38 110.25 118.13 126
Bytes DOS total 7518 6802 6444 6086
Bytes max 7692 7143 6667 6250
Byte Time: time between consecutive Byte Ready pulses
Sync Time: DOS 40-bits sync: (40-10+1.5) * Bit Time
Bytes DOS total: DOS track cap. needed (Sectors * total GCR)
Bytes max: track max. capacity (Byte Rate * rotation time)
Attention! The track capacity depends on actual drive speed (RPM)
Byte Ready
Byte is ready on falling edge, falling edge is latching data on Port A (VIA2).
$1C01 access resets Byte Ready U6 and CA1 in IFR, Port A (VIA2) latch resets.
$1C0x access (for $1C01 see above) resets Byte Ready U6 only, Port A latch holds.
1541 with UC1 325572 controller chip:
Byte Ready low time is typ. (Bit Time)/2 (see above)
1541B, 1541II, 1571 (1MHz mode) with UC4/U10/U6 64H156 (251828) controller chip:
Byte Ready low time is 1 or 2 or 3us
1571 (2MHz mode) with U6 64H156 (251828) controller chip:
Byte Ready is held low until VIA2 is accessed by read or write!
(see schematic U12 and TED input of U6)
This establishes a hand shake for Byte Ready. Benefit: Avoiding SW sampling and
Set Overflow issues.
Byte Ready could be missed when relying on sampling.
loop: BIT $180F (4 cycles)
BMI loop (3 cycles)
Total: 7 cycles -> 3.5us (2MHz mode)
Sampling every 3.5us won't work properly on bitrate2 and bitrate3 !!
Sync
Sync is going low after 10 consecutive '1' bits and staying low until the next '0' in the bit stream.
Its low time can range from Bit Time up to infinity (all sync track).
example 1:
Track data stream example, data ends on '0'
01100111010110101111111111111111111~111111101001101110
end of data---^ ^---start of data (framing)
_________________________ ___________
1234567890|<--sync signal-->|
remark: all consecutive 1-bits count (sync detection >=10)
example 2:
Track data stream example, data ends on '1'
01100111010110101111111111111111111~111111101001101110
end of data----^ ^---start of data (framing)
_________________________ ___________
1234567890|<--sync signal-->|
example 3:
Track data stream example, data ends on '1'
01100111010110101111111111111111111~111111101001101110
end of data-------^ ^---start of data (framing)
_________________________ ___________
1234567890|<--sync signal-->|
Pinout
6502
_____________
| |_| |
GND | 1 40 | /RES
RDY | 2 39 | PHI2>
<PHI1 | 3 38 | SO
/IRQ | 4 37 | <PHI0
N.C. | 5 36 | N.C.
/NMI | 6 35 | N.C.
SYNC | 7 34 | R/W
VCC | 8 33 | D0
A0 | 9 32 | D1
A1 | 10 31 | D2
A2 | 11 30 | D3
A3 | 12 29 | D4
A4 | 13 28 | D5
A5 | 14 27 | D6
A6 | 15 26 | D7
A7 | 16 25 | A15
A8 | 17 24 | A14
A9 | 18 23 | A13
A10 | 19 22 | A12
A11 | 20 21 | GND
|_____________|
6522 6526/8520
_____________ _____________
| |_| | | |_| |
GND | 1 40 | CA1 GND | 1 40 | CNT
PA0 | 2 39 | CA2 PA0 | 2 39 | SP
PA1 | 3 38 | RS0 PA1 | 3 38 | RS0
PA2 | 4 37 | RS1 PA2 | 4 37 | RS1
PA3 | 5 36 | RS2 PA3 | 5 36 | RS2
PA4 | 6 35 | RS3 PA4 | 6 35 | RS3
PA5 | 7 34 | /RES PA5 | 7 34 | /RES
PA6 | 8 33 | D0 PA6 | 8 33 | D0
PA7 | 9 32 | D1 PA7 | 9 32 | D1
PB0 | 10 31 | D2 PB0 | 10 31 | D2
PB1 | 11 30 | D3 PB1 | 11 30 | D3
PB2 | 12 29 | D4 PB2 | 12 29 | D4
PB3 | 13 28 | D5 PB3 | 13 28 | D5
PB4 | 14 27 | D6 PB4 | 14 27 | D6
PB5 | 15 26 | D7 PB5 | 15 26 | D7
PB6 | 16 25 | PHI2 PB6 | 16 25 | PHI2
PB7 | 17 24 | CS1 PB7 | 17 24 | CS1
CB1 | 18 23 | /CS2 /PC | 18 23 | /FLAG
CB2 | 19 22 | R/W TOD | 19 22 | R/W
VCC | 20 21 | /IRQ VCC | 20 21 | /IRQ
|_____________| |_____________|
WD1770/1772
_____________
| |_| |
/CS | 1 28 | INTRQ
R/W | 2 27 | DRQ
A0 | 3 26 | /DDEN
A1 | 4 25 | /WPRT
D0 | 5 24 | /IP
D1 | 6 23 | /TR00
D2 | 7 22 | WD
D3 | 8 21 | WG
D4 | 9 20 | MO
D5 | 10 19 | /RD
D6 | 11 18 | CLK
D7 | 12 17 | DIRC
/MR | 13 16 | STEP
GND | 14 15 | VCC
|_____________|
1541/1571 40/42 Pin Gate Arrays
64H105 64H156
325572-01 251828-01(251828-02)
1541/1541A/SX-64 1541B/1541C/1541-II/1571
_____________ _____________
| |_| | | |_| |
VCC | 1 40 | B TEST | 1 40(42) |-BYTE
-B | 2 39 |-BYTE YB0 | 2 39(41) | SOE
-Q | 3 38 | SOE YB1 | 3 38(40) | B
Q | 4 37 |-SYNC YB2 | 4 37(39) | CK
-MTR | 5 36 | OE YB3 | 5 36(38) |-XQ
-A | 6 35 | YB7 YB4 | 6 35(37) | Q
| 7 34 | YB6 YB5 | 7 34(36) | R/W
MTR | 8 33 | YB6 | 8 33(35) | LOCK
| 9 32 | YB5 YB7 | 9 32(34) | PLL
STP0 | 10 31 | YB4 GND | 10 31(33) | CLR
| 11 30 | YB3 STP1 | 11 30(32) | VCC
STP1 | 12 29 | YB2 STP0 | 12 29(31) |-XRW
| 13 28 | MTR | 13 28(30) | Y3
| 14 27 | YB1 -A | 14 27(29) | Y2
Y3 | 15 26 | YB0 DS0 | 15 26(28) | Y1
Y2 | 16 25 | Q-OUT DS1 | 16 25(27) | Y0
Y1 | 17 24 | D-IN -SYNC | 17 24(26) | ATN
Y0 | 18 23 | CLK-IN TED | 18 23(25) | ATNI
CLK | 19 22 | LOAD OE | 19 22(24) | ATNA
GND | 20 21 | CLR -ACCL | 20 21(23) | OSC
|_____________| VCC | (21) (22) | GND
|_____________|
1541C/1571 20 Pin Gate Array
Address Selector, Saddle Canceller, Motor Speed Compensator (PLL)
64H157
251829-01
_________
| |_| |
OSC | 1 20 | /RAME
SYNC | 2 19 | /IO1
DATA | 3 18 | /IO2
TEST | 4 17 | /CS1
GND | 5 16 | /CS2
A15 | 6 15 | VCC
A14 | 7 14 | /ROME
A13 | 8 13 | LOCK
A12 | 9 12 | PLL
A10 | 10 11 | CLR
|_________|
Port A VIA1 Data Register
6522 Data Port A
VIA1: $1801
(applies to 1571 only)
+----------+---------------------------------------------------+
| Bit 7 |I: BYTE READY |
| Bit 6 |O: UNUSED |
| Bit 5 |O: PHI2 clock selection |
| | 0 = 1 MHZ, 1 = 2 MHZ |
| Bit 4 |I: UNUSED |
| Bit 3 |I: UNUSED |
| Bit 2 |O: R/W HEAD selection |
| | 0 = SIDE 0 (bottom), 1 = SIDE 1 (top) |
| Bit 1 |O: Data Direction of the Bus Driver (FSM*) |
| | 0 = Input, 1 = Output |
| Bit 0 |I: 0 = TRACK0 |
+----------+---------------------------------------------------+
Port B VIA1 Data Register
6522 Data Port B
VIA1: $1800
(applies to 1541 and 1571)
+----------+---------------------------------------------------+
| Bit 7 |I: ATN IN (inverted bus ATN) |
| Bits 6-5 |I: Device address preset switches: |
| | 00 = #8, 01 = #9, 10 = #10, 11 = #11 |
| Bit 4 |O: ATN acknowledge OUT |
| | 0 = automatic acknowledge by hardware |
| Bit 3 |O: CLOCK OUT |
| Bit 2 |I: CLOCK IN |
| Bit 1 |O: DATA OUT |
| Bit 0 |I: DATA IN |
+----------+---------------------------------------------------+
Port B VIA2 Data Register
6522 Data Port B
VIA2: $1C00
(applies to 1541 and 1571)
+----------+---------------------------------------------------+
| Bit 7 |I: 0 = SYNC detected |
| Bits 6-5 |O: Disk R/W bit rates: |
| | 00 = 250000 bit/s (Tracks 31-35)* |
| | 01 = 266667 bit/s (Tracks 25-30)* |
| | 10 = 285714 bit/s (Tracks 18-24)* |
| | 11 = 307692 bit/s (Tracks 1-17)* |
| Bit 4 |I: Write Protect Sense: 0 = Disk is protected |
| Bit 3 |O: Drive LED: 1 = On |
| Bit 2 |O: Drive Motor: 1 = On |
| Bit 1-0 |O: Stepper motor control bits: |
| | Sequence 00/01/10/11/00... head moves inwards |
| | Sequence 00/11/10/01/00... head moves outwards |
+----------+---------------------------------------------------+
* for Tracks 36-70: calculate Track-35 (applies to 1571 only)
Auxiliary Control Register
6522 Auxiliary Control Register
VIA1: $180B
VIA2: $1C0B
(applies to 1541 and 1571)
+----------+---------------------------------------------------------+
| Bits 7-6 | Timer 1 Control: |
| | 00 = Timed Interrupt when Timer 1 is loaded, no PB7 |
| | 01 = Continuous Interrupts, no PB7 |
| | 10 = Timed Interrupt when Timer 1 is loaded, |
| | one-shot on PB7 |
| | 11 = Continuous Interrupts, square-wave on PB7 |
| Bit 5 | Timer 2 Control: 0 = Timed Interrupt |
| | 1 = Count Pulses on PB6 |
| Bits 4-2 | Shift Register Control: |
| | 000 = Disabled |
| | 001 = Shift in under control of Timer 2 |
| | 010 = Shift in under control of PHI2 |
| | 011 = Shift in under control of ext. Clock |
| | 100 = Shift out free-running at Timer 2 rate |
| | 101 = Shift out under control of Timer 2 |
| | 110 = Shift out under control of PHI2 |
| | 111 = Shift out under control of ext. Clock |
| Bit 1 | 1 = enable latching PB |
| Bit 0 | 1 = enable latching PA |
+----------+---------------------------------------------------------+
Peripheral Control Register
6522 Peripheral Control Register
VIA1: $180C
VIA2: $1C0C
(applies to 1541 and 1571)
+----------+-----------------------------------------------------+
| Bits 7-5 | CB2 Control: |
| | 000 = Input negative active edge |
| | 001 = Independent interrupt input negative edge |
| | 010 = Input positive active edge |
| | 011 = Independent interrupt input positive edge |
| | 100 = Handshake output |
| | 101 = Pulse output |
| | 110 = Low output |
| | 111 = High output |
| Bit 4 | CB1 Interrupt Control: 0 = Negative active edge |
| | 1 = Positive active edge |
| Bit 3-1 | CA2 Control: see Bits 7-5 |
| Bit 0 | CA1 Interrupt Control: see Bit 4 |
+----------+-----------------------------------------------------+
Interrupt Flag Register
6522 Interrupt Flag Register
VIA1: $180D
VIA2: $1C0D
(applies to 1541 and 1571)
+-------+------------------------------------------------------+
| Bit 7 | 1 = Interrupt request |
| Bit 6 | Timer 1 |
| Bit 5 | Timer 2 |
| Bit 4 | CB1 |
| Bit 3 | CB2 |
| Bit 2 | Shift Register |
| Bit 1 | CA1 |
| Bit 0 | CA2 |
+-------+------------------------------------------------------+
Write: any '1' bit will clear corresponding flag
IFR SET BY | IFR CLEARED BY
----------------------+-----------------------
CA2 active edge | Read or write (ORA*)
CA1 active edge | Read or write (ORA*)
Complete 8 shifts | Read or write Shift Register
CB2 active edge | Read or write (ORB*)
CB1 active edge | Read or write ORB
Time-out of T2 | Read T2 low or write T2 high
Time-out of T1 | Read T1C-L low or write T1L-H high
Any enabled interrupt | Clear all interrupts
*If the CA2/CB2 control in the PCR is selected as "independent" interrupt input, then reading or writing the output register ORA/ORB will not clear the flag bit. Instead, the bit must be cleared by writing into the IFR.
Interrupt Enable Register
6522 Interrupt Enable Register
VIA1: $180E
VIA2: $1C0E
(applies to 1541 and 1571)
+-------+------------------------------------------------------+
| Bit 7 | Write (Mask-Bits 6-0): |
| | If Mask-Bit=1 and Bit 7=1: enable IRQ |
| | If Mask-Bit=1 and Bit 7=0: disable IRQ |
| Bit 6 | Timer 1 |
| Bit 5 | Timer 2 |
| Bit 4 | CB1 |
| Bit 3 | CB2 |
| Bit 2 | Shift Register |
| Bit 1 | CA1 |
| Bit 0 | CA2 |
+-------+------------------------------------------------------+
Port A CIA Data Register
6526 Data Port A
CIA: $4000
(applies to 1581 only, not used on 1571)
+----------+---------------------------------------------------+
| Bit 7 |I: 0 = Disk Change (will be reset after the |
| | next move of the head) |
| Bit 6 |O: 1 = Drive LED on |
| Bit 5 |O: 1 = Error LED bright |
| Bits 4+3 |I: DIP Switches for Device Number |
| | 00 = #8, 01 = #9, 10 = #10, 11 = #11 |
| Bit 2 |O: 0 = Motor on |
| Bit 1 |I: 0 = Ready (Disk inserted & motor on RPM) |
| Bit 0 |O: R/W head selection |
| | 1 = SIDE 0, 0 = SIDE 1 |
+----------+---------------------------------------------------+
Port B CIA Data Register
6526 Data Port B
CIA: $4001
(applies to 1581 only, not used on 1571)
+-------+------------------------------------------------------+
| Bit 7 |I: ATN IN |
| Bit 6 |I: Write Protect Sense: 0 = Disk is protected |
| Bit 5 |O: Data Direction of the Bus Driver (FSM)* |
| | 0 = Input, 1 = Output |
| Bit 4 |O: 1 = automatic ATN-Response |
| Bit 3 |O: CLOCK OUT |
| Bit 2 |I: CLOCK IN |
| Bit 1 |O: DATA OUT |
| Bit 0 |I: DATA IN |
+-------+------------------------------------------------------+
* FSM=Fast Serial Bus Mode, additional clock line SRQ is used